Sun 4 Nov 2018 16:15 - 16:40 at Stuart - II Chair(s): Adam Welc

Field-Programmable Gate Arrays (Fig’s) have been around since the early 1980s and have now achieved relatively wide-spread use. For example, FPGAs are routinely used for high-performance computing, financial applications, seismic modelling, DNA sequence alignment, software defined networking and, occasionally, are even found in smartphones. And yet, despite their success, there still remains something of a gap between programming languages and circuit designs for an FPGA. We consider the compilation of an imperative programming language, Whiley, to VHDL for use on an FPGA. Whiley supports compile-time verification of function pre- and post-conditions. Hence, our motivation is to adapt this technology for verifying properties of hardware designs.

Presentation (slides.pdf)1.18MiB

Sun 4 Nov

15:30 - 17:05: VMIL 2018 - II at Stuart
Chair(s): Adam WelcUber Technologies
vmil-201815:30 - 15:55
Research paper
Baptiste SaleilUniversité de Montréal, Marc FeeleyUniversité de Montréal
vmil-201815:55 - 16:15
Julien PagèsUniversité de Montréal, Marc FeeleyUniversité de Montréal
vmil-201816:15 - 16:40
Research paper
Baptiste PaugetÉcole Normale Supérieure, David PearceVictoria University of Wellington, Alex PotaninVictoria University of Wellington
DOI Pre-print File Attached
vmil-201816:40 - 17:05
Research paper
Eliot MirandaCadence Design Systems, Clément BéraSofware Languages Lab, Vrije Universiteit Brussel, Elisa Gonzalez BoixVrije Universiteit Brussel, Dan Ingalls