PyGA: A Python to FPGA compiler prototype
Field Programmable Gate Arrays, FPGAs, are a widely available configurable hardware design that is commonly used in many domain-specific applications. However, the complexity of its programming interface is currently restricting its usage to highly qualified programmers dedicated to FPGA. In order to democratize FPGAs, many efforts are concentrating on High-Level Synthesis, HLS: the process of compiling a more general language. In that context we propose in this paper PyGA, a proof of concept of a Python to FPGA compiler based on the Numba Just-In-Time (JIT) compiler for Python and the Intel FPGA SDK for OpenCL. It allows any Python user to use a FPGA card as an accelerator for Python seamlessly. As expected, early performance results are encouraging, but not competitive with compiled CPU version. It emphasis that, to avoid overhead that cannot be compensated otherwise, tightly coupled accelerator design such as Intel Xeon+FPGA are necessary to address larger code base with finer grain kernel. It also shows that HLS compilation and runtime efforts remains to be done to be competitive with modern multi-core CPUs.
Tue 6 NovDisplayed time zone: Guadalajara, Mexico City, Monterrey change
08:00 - 10:00 | AI SEPSAI-SEPS at Cabot Chair(s): Ali Jannesari Iowa State University, Yukinori Sato Toyohashi University of Technology | ||
08:00 50mTalk | Deep Learning at ScaleKeynote AI-SEPS Prabhat NERSC, Berkeley Lab | ||
08:50 25mTalk | PIRA: Performance Instrumentation Refinement Automation AI-SEPS Jan-Patrick Lehr Graduate School of Computational Engineering, TU Darmstadt, Alexander Hück Institute for Scientific Computing, TU Darmstadt, Christian Bischof Scientific Computing, TU Darmstadt | ||
09:15 15mTalk | PyGA: A Python to FPGA compiler prototype AI-SEPS | ||
09:30 30mTalk | Panel discussion AI-SEPS P: Yukinori Sato Toyohashi University of Technology, P: Ali Jannesari Iowa State University, P: Shigeru Chiba The University of Tokyo |